The present invention generally relates to a non-volatile semiconductor memory device and non-volatile semiconductor memory devices having improved erase speed and/or less bit line leakage, and methods of forming such memory devices.
Conventional floating gate flash memory types of EEPROMs (electrically erasable programmable read only memory), employ a memory cell characterized by a vertical stack of a tunnel oxide, a first polysilicon layer over the tunnel oxide, an ONO (oxide-nitride-oxide) interlevel dielectric over the first polysilicon layer, and a second polysilicon layer over the ONO interlevel dielectric. For example, Guterman et al (IEEE Transactions on Electron Devices, Vol. 26, No. 4, p. 576, 1979) relates to a floating gate nonvolatile memory cell consisting of a floating gate sandwiched between a gate oxide and an interlevel oxide, with a control gate over the interlevel oxide.
Generally speaking, a flash memory cell is programmed by inducing hot electron injection from a portion of the substrate, such as the channel section near the drain region, to the floating gate. Electron injection carries negative charge into the floating gate. The injection mechanism can be induced by grounding the source region and a bulk portion of the substrate and applying a relatively high positive voltage to the control electrode to create an electron attracting field and applying a positive voltage of moderate magnitude to the drain region in order to generate xe2x80x9chotxe2x80x9d (high energy) electrons. After sufficient negative charge accumulates on the floating gate, the negative potential of the floating gate raises the threshold voltage of its field effect transistor (FET) and inhibits current flow through the channel region through a subsequent xe2x80x9creadxe2x80x9d mode. The magnitude of the read current is used to determine whether or not a flash memory cell is programmed.
The act of discharging the floating gate of a flash memory cell is called the erase function. The erase function is typically carried out by a Fowler-Nordheim tunneling mechanism between the floating gate and the source region of the transistor (source erase or negative gate erase) or between the floating gate and the substrate (channel erase). A source erase operation is induced by applying a high positive voltage to the source region and a 0 V to the control gate and the substrate while floating the drain of the respective memory cell.
Subsequently, SONOS (Silicon Oxide Nitride Oxide Silicon) type memory devices have been introduced. See Chan et al, IEEE Electron Device Letters, Vol. 8, No. 3, p. 93, 1987. SONOS type flash memory cells are constructed having a charge trapping non-conducting dielectric layer, typically a silicon nitride layer, sandwiched between two silicon dioxide layers (insulating layers). The nonconducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. Since the electrical charge is trapped locally near whichever side that is used as the drain, this structure can be described as a two-transistor cell, or two-bits per cell. If multi-level is used, then four or more bits per cell can be accomplished. Multi-bit cells enable SONOS type memory devices to have the advantage over others in facilitating the continuing trend increasing the amount of information held/processed on an integrated circuit chip.
For simplicity, a two-bit per cell implementation of SONOS is described. While both bits of SONOS type memory devices are programmed in a conventional manner, such as using hot electron programming, each bit is read in a direction opposite that in which it is programmed with a relatively low gate voltage. For example, the right bit is programmed conventionally by applying programming voltages to the gate and the drain while the source is grounded or at a lower voltage. Hot electrons are accelerated sufficiently so that they are injected into a region of the trapping dielectric layer near the drain. The device, however, is read in the opposite direction from which it is written, meaning voltages are applied to the gate and the source while the drain is grounded or at a lower voltage. The left bit is similarly programmed and read by swapping the functionality of source and drain terminals. Programming one of the bits leaves the other bit with its information intact and undisturbed. Programming one of the bits may have a very small effect on the other bit.
Reading in the reverse direction is most effective when relatively low gate voltages are used. A benefit of utilizing relatively low gate voltages in combination with reading in the reverse direction is that the potential drop across the portion of the channel beneath the trapped charge region is significantly reduced. A relatively small programming region or charge trapping region is possible due to the lower channel potential drop under the charge trapping region. This permits much faster programming times because the effect of the charge trapped in the localized trapping region is amplified. Programming times are reduced while the delta in threshold voltage between the programmed versus unprogrammed states remains the same as when the device is read in the forward direction.
SONOS type memory devices offer additional advantages as well. In particular, the erase mechanism of the memory cell is greatly enhanced. Both bits of the memory cell can be erased by applying suitable erase voltages to the gate and the drain for the right bit and to the gate and the source for the left bit. Another advantage includes reduced wearout from cycling thus increasing device longevity. An effect of reading in the reverse direction is that a much higher threshold voltage for the same amount of programming is possible. Thus, to achieve a sufficient delta in the threshold voltage between the programmed and unprograrmed states of the memory cell, a much smaller region of trapped charge is required when the cell is read in the reverse direction than when the cell is read in the forward direction.
The erase mechanism is enhanced when the charge trapping region is made as narrow as possible. Programming in the forward direction and reading in the reverse direction permits limiting the width of the charge trapping region to a narrow region near the drain (right bit) or the source. This allows for much more efficient erasing of the memory cell.
Another advantage of localized charge trapping is that during erase, the region of the nitride away from the drain does not experience deep depletion since the erase occurs near the drain only. The final threshold of the cell after erasing is self limited by the device structure itself. This is in direct contrast to conventional single transistor floating gate flash memory cells which often have deep depletion problems.
Although many advantages are described above, there are at least two disadvantages associated with SONOS type memory devices. One disadvantage is that slow and/or non-uniform erase times are exhibited by certain memory cells. In some instances, a build-up of charges in or near the floating gate of some of the memory cells in an array after cycling undesirably causes an increase in erase time for these particular memory cells. Moreover, memory cells having gates with different widths have different erase speeds. In this connection, gate transistors with relatively wide widths generally have slower erase speeds.
One characteristic of a SONOS type non-volatile memory devices is erase speed. There is an unmet need for SONOS type non-volatile memory devices that exhibit fast erase times as well as uniform erase times across an array. Fast and uniform erase times facilitate reliability and the processing of increased amounts of information in a set period of time.
Another disadvantage with SONOS type memory devices is bit line leakage. While bit line leakage may occur anywhere within an array of memory cells, it is especially likely to occur at the tip or end of the bitlines and/or near contacts. Thermal cycling associated with LOCOS (LOCal Oxidation of Silicon) formation may cause an increase in bitline to bitline punch-through leakage. That is, implant diffusion caused by thermal cycling may lead to undesirable leakage between bitlines. There is an unmet need for SONOS type non-volatile memory devices that exhibit less bitline leakage.
The present invention provides SONOS type non-volatile semiconductor memory devices characterized by improved erase times and less bitline leakage. The SONOS type non-volatile semiconductor memory devices of the present invention have at least one dummy wordline positioned near the edge of a memory cell array and/or near one or more bitline contacts within the memory cell array. Improved erase times means that at least one of faster erase times and erase times of increased uniformity for all memory cells with an array.
One aspect of the present invention relates to a SONOS type non-volatile semiconductor memory device, containing a silicon substrate comprising a core region and periphery region, the core region comprising a plurality of memory cells and bitlines extending in a first direction; each of the plurality of memory cells comprising a charge trapping layer over the silicon substrate, and a polysilicon layer over the charge trapping layer; wordlines extending in a second direction, the wordlines comprising functioning wordlines and at least one dummy wordline, wherein the dummy wordline is positioned near at least one of a bitline contact and an edge of the core region, and the dummy wordline is treated so as not to cycle between on and off states.
Another aspect of the present invention relates to a SONOS type non-volatile semiconductor memory cell having improved erase speed, containing a silicon substrate comprising a core region and periphery region, the core region comprising at least one array of memory cells and the periphery region comprising input/output circuitry; each of the memory cells comprising a charge trapping layer over the silicon substrate, and a polysilicon layer over the charge trapping layer, the core region comprising a plurality of bitlines extending in a first direction; the core region comprising a plurality of wordlines extending in a second direction, the wordlines comprising functioning wordlines and at least one dummy wordline, wherein the dummy wordline is positioned between the functioning wordlines and the periphery region, and the dummy wordline is treated so as not to cycle between on and off states.
Yet another aspect of the present invention relates to a method of making a SONOS type non-volatile semiconductor memory device, involving providing a silicon substrate having a core region and a periphery region; forming at least one array of memory cells in the core region, the memory cells comprising a charge trapping layer over the silicon substrate, and a polysilicon layer over the charge trapping layer; forming a plurality of bitlines extending in a first direction in the core region; forming a plurality of functioning wordlines extending in a second direction in the core region; forming at least one dummy wordline between the functioning wordlines and the periphery region or between the functioning wordlines and a bitline contact and treating the device so that the dummy wordline does not cycle between on and off states.
Still yet another aspect of the present invention relates to a method of increasing erase speed in a SONOS type non-volatile memory device, involving providing a silicon substrate having a core region and a periphery region, the core region comprising at least one array of memory cells, the memory cells comprising an ONO charge trapping layer over the silicon substrate, and a polysilicon layer over the ONO charge trapping layer, a plurality of bitlines extending in a first direction, a plurality of functioning wordlines extending in a second direction; forming at least one dummy wordline between the functioning wordlines and the periphery region or between the functioning wordlines and a bitline contact and treating the device so that the dummy wordline does not cycle between on and off states.